what is the current execution mode/exception level, etc?
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I am new to ARMv8 architecture. I have following basic questions on my mind:
How do I know what is the current execution mode AArch32 or AArch64? Should I read CPSR or SPSR to ascertain this?
What is the current Exception level, EL0/1/2/3?
Once an exception comes, can i read any register to determine whether I am in Serror/Synchronous/IRQ/FIQ exception handler.
TIA.
exception-handling arm arm64
asked Aug 3 '15 at 12:43
chetanchetan
498
add a comment |
2
I am new to ARMv8 architecture. I have following basic questions on my mind:
How do I know what is the current execution mode AArch32 or AArch64? Should I read CPSR or SPSR to ascertain this?
What is the current Exception level, EL0/1/2/3?
Once an exception comes, can i read any register to determine whether I am in Serror/Synchronous/IRQ/FIQ exception handler.
TIA.
exception-handling arm arm64
asked Aug 3 '15 at 12:43
chetanchetan
498
2
"How do I know what is the current execution mode AArch32 or AArch64?" - I figure if the the code trying to check the mode is compiled for 64-bit, the mode is 64-bit; if it's compiled for 32-bit the mode is 32-bit.
– JimmyB
Aug 3 '15 at 12:59
add a comment |
2
2
2
I am new to ARMv8 architecture. I have following basic questions on my mind:
How do I know what is the current execution mode AArch32 or AArch64? Should I read CPSR or SPSR to ascertain this?
What is the current Exception level, EL0/1/2/3?
Once an exception comes, can i read any register to determine whether I am in Serror/Synchronous/IRQ/FIQ exception handler.
TIA.
exception-handling arm arm64
asked Aug 3 '15 at 12:43
chetanchetan
498
I am new to ARMv8 architecture. I have following basic questions on my mind:
How do I know what is the current execution mode AArch32 or AArch64? Should I read CPSR or SPSR to ascertain this?
What is the current Exception level, EL0/1/2/3?
Once an exception comes, can i read any register to determine whether I am in Serror/Synchronous/IRQ/FIQ exception handler.
TIA.
exception-handling arm arm64
exception-handling arm arm64
asked Aug 3 '15 at 12:43
chetanchetan
498
asked Aug 3 '15 at 12:43
chetanchetan
498
asked Aug 3 '15 at 12:43
chetanchetan
498
asked Aug 3 '15 at 12:43
chetanchetan
498
asked Aug 3 '15 at 12:43
chetanchetan
498
498
2
"How do I know what is the current execution mode AArch32 or AArch64?" - I figure if the the code trying to check the mode is compiled for 64-bit, the mode is 64-bit; if it's compiled for 32-bit the mode is 32-bit.
– JimmyB
Aug 3 '15 at 12:59
add a comment |
2
"How do I know what is the current execution mode AArch32 or AArch64?" - I figure if the the code trying to check the mode is compiled for 64-bit, the mode is 64-bit; if it's compiled for 32-bit the mode is 32-bit.
– JimmyB
Aug 3 '15 at 12:59
2
2
"How do I know what is the current execution mode AArch32 or AArch64?" - I figure if the the code trying to check the mode is compiled for 64-bit, the mode is 64-bit; if it's compiled for 32-bit the mode is 32-bit.
– JimmyB
Aug 3 '15 at 12:59
"How do I know what is the current execution mode AArch32 or AArch64?" - I figure if the the code trying to check the mode is compiled for 64-bit, the mode is 64-bit; if it's compiled for 32-bit the mode is 32-bit.
– JimmyB
Aug 3 '15 at 12:59
add a comment |
2 Answers
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5
- The assembly instructions and their binary encoding are entirely different for 32 and 64 bit. So the information what mode you are currently in is something that you/ the compiler already needs to know during compilation. checking for them at runtime doesn't make sense. For C, C++ checking can be done at compile time (
#ifdef) through compiler provided macros like the ones provided byarmclang:__aarch64__for 64 bit,__arm__for 32 bit - depends on the execution mode:
- aarch32:
MRS <Rn>, CPSRread the current state into register number n. Then extract bits 3:0 that contain the current mode. - aarch64:
MRS <Xn>, CurrentELread the current EL into register number n
- aarch32:
- short answer: you can't. long answer: the assumption is that by the structure of the code and the state of any user defined variables, you already know what you are doing. i.e. whether you came to a position in code through regular code or through an exception.
answered Aug 3 '15 at 15:48
Martin KeßlerMartin Keßler
322138
For the 2nd point I am able to find the current mode when I am in EL1, EL2, or EL3 mode by reading through CPSR register. However, if I am in EL0 mode reading cpsr causes exception.
– chetan
May 4 '16 at 9:00
@chetan: "if I am in EL0 mode reading cpsr causes exception." AFAIK, that of course is the whole point! EL0 is the unprivileged 'app' mode; apps cannot/must not have access to info like this..So, my understanding is, write a kernel module to read register values. It should work as it runs in EL1, if not EL2.
– kaiwan
Jul 27 '17 at 6:30
add a comment |
1
aarch64 C code:
register uint64_t x0 __asm__ ("x0");
__asm__ ("mrs x0, CurrentEL;" : : : "%x0");
printf("EL = %" PRIu64 "n", x0 >> 2);
arm C code:
register uint32_t r0 __asm__ ("r0");
__asm__ ("mrs r0, CPSR" : : : "%r0");
printf("EL = %" PRIu32 "n", r0 & 0x1F);
Those registers are normally (always?) protected in userland though, so you must to this from the Linux kernel or a baremetal example.
Tested on QEMU and gem5 with this setup.
answered Nov 23 '18 at 11:30
Ciro SantilliCiro Santilli
760218
add a comment |
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2 Answers
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2 Answers
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active
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5
- The assembly instructions and their binary encoding are entirely different for 32 and 64 bit. So the information what mode you are currently in is something that you/ the compiler already needs to know during compilation. checking for them at runtime doesn't make sense. For C, C++ checking can be done at compile time (
#ifdef) through compiler provided macros like the ones provided byarmclang:__aarch64__for 64 bit,__arm__for 32 bit - depends on the execution mode:
- aarch32:
MRS <Rn>, CPSRread the current state into register number n. Then extract bits 3:0 that contain the current mode. - aarch64:
MRS <Xn>, CurrentELread the current EL into register number n
- aarch32:
- short answer: you can't. long answer: the assumption is that by the structure of the code and the state of any user defined variables, you already know what you are doing. i.e. whether you came to a position in code through regular code or through an exception.
answered Aug 3 '15 at 15:48
Martin KeßlerMartin Keßler
322138
For the 2nd point I am able to find the current mode when I am in EL1, EL2, or EL3 mode by reading through CPSR register. However, if I am in EL0 mode reading cpsr causes exception.
– chetan
May 4 '16 at 9:00
@chetan: "if I am in EL0 mode reading cpsr causes exception." AFAIK, that of course is the whole point! EL0 is the unprivileged 'app' mode; apps cannot/must not have access to info like this..So, my understanding is, write a kernel module to read register values. It should work as it runs in EL1, if not EL2.
– kaiwan
Jul 27 '17 at 6:30
add a comment |
5
- The assembly instructions and their binary encoding are entirely different for 32 and 64 bit. So the information what mode you are currently in is something that you/ the compiler already needs to know during compilation. checking for them at runtime doesn't make sense. For C, C++ checking can be done at compile time (
#ifdef) through compiler provided macros like the ones provided byarmclang:__aarch64__for 64 bit,__arm__for 32 bit - depends on the execution mode:
- aarch32:
MRS <Rn>, CPSRread the current state into register number n. Then extract bits 3:0 that contain the current mode. - aarch64:
MRS <Xn>, CurrentELread the current EL into register number n
- aarch32:
- short answer: you can't. long answer: the assumption is that by the structure of the code and the state of any user defined variables, you already know what you are doing. i.e. whether you came to a position in code through regular code or through an exception.
answered Aug 3 '15 at 15:48
Martin KeßlerMartin Keßler
322138
For the 2nd point I am able to find the current mode when I am in EL1, EL2, or EL3 mode by reading through CPSR register. However, if I am in EL0 mode reading cpsr causes exception.
– chetan
May 4 '16 at 9:00
@chetan: "if I am in EL0 mode reading cpsr causes exception." AFAIK, that of course is the whole point! EL0 is the unprivileged 'app' mode; apps cannot/must not have access to info like this..So, my understanding is, write a kernel module to read register values. It should work as it runs in EL1, if not EL2.
– kaiwan
Jul 27 '17 at 6:30
add a comment |
5
5
5
- The assembly instructions and their binary encoding are entirely different for 32 and 64 bit. So the information what mode you are currently in is something that you/ the compiler already needs to know during compilation. checking for them at runtime doesn't make sense. For C, C++ checking can be done at compile time (
#ifdef) through compiler provided macros like the ones provided byarmclang:__aarch64__for 64 bit,__arm__for 32 bit - depends on the execution mode:
- aarch32:
MRS <Rn>, CPSRread the current state into register number n. Then extract bits 3:0 that contain the current mode. - aarch64:
MRS <Xn>, CurrentELread the current EL into register number n
- aarch32:
- short answer: you can't. long answer: the assumption is that by the structure of the code and the state of any user defined variables, you already know what you are doing. i.e. whether you came to a position in code through regular code or through an exception.
answered Aug 3 '15 at 15:48
Martin KeßlerMartin Keßler
322138
- The assembly instructions and their binary encoding are entirely different for 32 and 64 bit. So the information what mode you are currently in is something that you/ the compiler already needs to know during compilation. checking for them at runtime doesn't make sense. For C, C++ checking can be done at compile time (
#ifdef) through compiler provided macros like the ones provided byarmclang:__aarch64__for 64 bit,__arm__for 32 bit - depends on the execution mode:
- aarch32:
MRS <Rn>, CPSRread the current state into register number n. Then extract bits 3:0 that contain the current mode. - aarch64:
MRS <Xn>, CurrentELread the current EL into register number n
- aarch32:
- short answer: you can't. long answer: the assumption is that by the structure of the code and the state of any user defined variables, you already know what you are doing. i.e. whether you came to a position in code through regular code or through an exception.
answered Aug 3 '15 at 15:48
Martin KeßlerMartin Keßler
322138
answered Aug 3 '15 at 15:48
Martin KeßlerMartin Keßler
322138
answered Aug 3 '15 at 15:48
Martin KeßlerMartin Keßler
322138
answered Aug 3 '15 at 15:48
Martin KeßlerMartin Keßler
322138
322138
For the 2nd point I am able to find the current mode when I am in EL1, EL2, or EL3 mode by reading through CPSR register. However, if I am in EL0 mode reading cpsr causes exception.
– chetan
May 4 '16 at 9:00
@chetan: "if I am in EL0 mode reading cpsr causes exception." AFAIK, that of course is the whole point! EL0 is the unprivileged 'app' mode; apps cannot/must not have access to info like this..So, my understanding is, write a kernel module to read register values. It should work as it runs in EL1, if not EL2.
– kaiwan
Jul 27 '17 at 6:30
add a comment |
For the 2nd point I am able to find the current mode when I am in EL1, EL2, or EL3 mode by reading through CPSR register. However, if I am in EL0 mode reading cpsr causes exception.
– chetan
May 4 '16 at 9:00
@chetan: "if I am in EL0 mode reading cpsr causes exception." AFAIK, that of course is the whole point! EL0 is the unprivileged 'app' mode; apps cannot/must not have access to info like this..So, my understanding is, write a kernel module to read register values. It should work as it runs in EL1, if not EL2.
– kaiwan
Jul 27 '17 at 6:30
For the 2nd point I am able to find the current mode when I am in EL1, EL2, or EL3 mode by reading through CPSR register. However, if I am in EL0 mode reading cpsr causes exception.
– chetan
May 4 '16 at 9:00
For the 2nd point I am able to find the current mode when I am in EL1, EL2, or EL3 mode by reading through CPSR register. However, if I am in EL0 mode reading cpsr causes exception.
– chetan
May 4 '16 at 9:00
@chetan: "if I am in EL0 mode reading cpsr causes exception." AFAIK, that of course is the whole point! EL0 is the unprivileged 'app' mode; apps cannot/must not have access to info like this..So, my understanding is, write a kernel module to read register values. It should work as it runs in EL1, if not EL2.
– kaiwan
Jul 27 '17 at 6:30
@chetan: "if I am in EL0 mode reading cpsr causes exception." AFAIK, that of course is the whole point! EL0 is the unprivileged 'app' mode; apps cannot/must not have access to info like this..So, my understanding is, write a kernel module to read register values. It should work as it runs in EL1, if not EL2.
– kaiwan
Jul 27 '17 at 6:30
add a comment |
1
aarch64 C code:
register uint64_t x0 __asm__ ("x0");
__asm__ ("mrs x0, CurrentEL;" : : : "%x0");
printf("EL = %" PRIu64 "n", x0 >> 2);
arm C code:
register uint32_t r0 __asm__ ("r0");
__asm__ ("mrs r0, CPSR" : : : "%r0");
printf("EL = %" PRIu32 "n", r0 & 0x1F);
Those registers are normally (always?) protected in userland though, so you must to this from the Linux kernel or a baremetal example.
Tested on QEMU and gem5 with this setup.
answered Nov 23 '18 at 11:30
Ciro SantilliCiro Santilli
760218
add a comment |
1
aarch64 C code:
register uint64_t x0 __asm__ ("x0");
__asm__ ("mrs x0, CurrentEL;" : : : "%x0");
printf("EL = %" PRIu64 "n", x0 >> 2);
arm C code:
register uint32_t r0 __asm__ ("r0");
__asm__ ("mrs r0, CPSR" : : : "%r0");
printf("EL = %" PRIu32 "n", r0 & 0x1F);
Those registers are normally (always?) protected in userland though, so you must to this from the Linux kernel or a baremetal example.
Tested on QEMU and gem5 with this setup.
answered Nov 23 '18 at 11:30
Ciro SantilliCiro Santilli
760218
add a comment |
1
1
1
aarch64 C code:
register uint64_t x0 __asm__ ("x0");
__asm__ ("mrs x0, CurrentEL;" : : : "%x0");
printf("EL = %" PRIu64 "n", x0 >> 2);
arm C code:
register uint32_t r0 __asm__ ("r0");
__asm__ ("mrs r0, CPSR" : : : "%r0");
printf("EL = %" PRIu32 "n", r0 & 0x1F);
Those registers are normally (always?) protected in userland though, so you must to this from the Linux kernel or a baremetal example.
Tested on QEMU and gem5 with this setup.
answered Nov 23 '18 at 11:30
Ciro SantilliCiro Santilli
760218
aarch64 C code:
register uint64_t x0 __asm__ ("x0");
__asm__ ("mrs x0, CurrentEL;" : : : "%x0");
printf("EL = %" PRIu64 "n", x0 >> 2);
arm C code:
register uint32_t r0 __asm__ ("r0");
__asm__ ("mrs r0, CPSR" : : : "%r0");
printf("EL = %" PRIu32 "n", r0 & 0x1F);
Those registers are normally (always?) protected in userland though, so you must to this from the Linux kernel or a baremetal example.
Tested on QEMU and gem5 with this setup.
answered Nov 23 '18 at 11:30
Ciro SantilliCiro Santilli
760218
edited Nov 23 '18 at 11:36
answered Nov 23 '18 at 11:30
Ciro SantilliCiro Santilli
760218
answered Nov 23 '18 at 11:30
Ciro SantilliCiro Santilli
760218
answered Nov 23 '18 at 11:30
Ciro SantilliCiro Santilli
760218
760218
add a comment |
add a comment |
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2
"How do I know what is the current execution mode AArch32 or AArch64?" - I figure if the the code trying to check the mode is compiled for 64-bit, the mode is 64-bit; if it's compiled for 32-bit the mode is 32-bit.
– JimmyB
Aug 3 '15 at 12:59