Makefile: variables are not included from other makefile
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I want to use a common.mk file for common variable definitions and include this file in other Makefiles but in the first example I've done it is not working so I think that I have misunderstood something.
This is the Makefile:
CC=gcc
CFLAGS=-g -Wall
LIB_FLAGS=-L/usr/local/lib/ -lcgreen
BUILDDIR=$(CURDIR)/build
SRC=$(wildcard *.c)
export BUILDDIR
export CFLAGS
export LIB_FLAGS
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
unittests: dir externals $(OBJ)
@echo "SRC: $(SRC)"
@echo "OBJ: $(OBJ)" # THIS PRINTS OBJ AS EMPTY <------------------------------
$(CC) $(BUILDDIR)/*.o $(LIB_FLAGS) -o $(BUILDDIR)/unittests
$(BUILDDIR)/unittests
externals:
@$(MAKE) -C lib1 -f lib1.mk
dir:
mkdir -p $(BUILDDIR)
This is the common.mk file:
OBJ=$(patsubst %.c, $(BUILDDIR)/%.o, $(notdir $(SRC)))
$(BUILDDIR)/%.o: %.c
@echo "File: "$<
$(CC) -c $(CFLAGS) $< -o $@
clean:
rm -f $(OBJ)
So I was expecting that the OBJ variable in the main Makefile had a object files list but it is empty and I don't understand why. Isn't it including the common.mk file the same as copying it's content into the Makefile?
Thanks
makefile gnu-make
add a comment |
up vote
0
down vote
favorite
I want to use a common.mk file for common variable definitions and include this file in other Makefiles but in the first example I've done it is not working so I think that I have misunderstood something.
This is the Makefile:
CC=gcc
CFLAGS=-g -Wall
LIB_FLAGS=-L/usr/local/lib/ -lcgreen
BUILDDIR=$(CURDIR)/build
SRC=$(wildcard *.c)
export BUILDDIR
export CFLAGS
export LIB_FLAGS
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
unittests: dir externals $(OBJ)
@echo "SRC: $(SRC)"
@echo "OBJ: $(OBJ)" # THIS PRINTS OBJ AS EMPTY <------------------------------
$(CC) $(BUILDDIR)/*.o $(LIB_FLAGS) -o $(BUILDDIR)/unittests
$(BUILDDIR)/unittests
externals:
@$(MAKE) -C lib1 -f lib1.mk
dir:
mkdir -p $(BUILDDIR)
This is the common.mk file:
OBJ=$(patsubst %.c, $(BUILDDIR)/%.o, $(notdir $(SRC)))
$(BUILDDIR)/%.o: %.c
@echo "File: "$<
$(CC) -c $(CFLAGS) $< -o $@
clean:
rm -f $(OBJ)
So I was expecting that the OBJ variable in the main Makefile had a object files list but it is empty and I don't understand why. Isn't it including the common.mk file the same as copying it's content into the Makefile?
Thanks
makefile gnu-make
1
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
doesn't include anything. It starts with#
, so it's just a comment.
– melpomene
Nov 19 at 19:13
@melpomene Thanks.. I am used to C and didn't notice it.. two hours lost because of that! so embarrasing.. Ouch!
– jap jap
Nov 19 at 19:16
1
If you use an editor which has some sort of makefile editing mode it will show comments in a different color. It will also do better at handling TAB vs. spaces, typically. For debugging it can be helpful to add$(info ...)
functions into your makefiles to show variable values at various times etc. Adding these intocommon.mk
would have probably let you know that it wasn't being parsed at all, pretty quickly.
– MadScientist
Nov 19 at 19:21
add a comment |
up vote
0
down vote
favorite
up vote
0
down vote
favorite
I want to use a common.mk file for common variable definitions and include this file in other Makefiles but in the first example I've done it is not working so I think that I have misunderstood something.
This is the Makefile:
CC=gcc
CFLAGS=-g -Wall
LIB_FLAGS=-L/usr/local/lib/ -lcgreen
BUILDDIR=$(CURDIR)/build
SRC=$(wildcard *.c)
export BUILDDIR
export CFLAGS
export LIB_FLAGS
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
unittests: dir externals $(OBJ)
@echo "SRC: $(SRC)"
@echo "OBJ: $(OBJ)" # THIS PRINTS OBJ AS EMPTY <------------------------------
$(CC) $(BUILDDIR)/*.o $(LIB_FLAGS) -o $(BUILDDIR)/unittests
$(BUILDDIR)/unittests
externals:
@$(MAKE) -C lib1 -f lib1.mk
dir:
mkdir -p $(BUILDDIR)
This is the common.mk file:
OBJ=$(patsubst %.c, $(BUILDDIR)/%.o, $(notdir $(SRC)))
$(BUILDDIR)/%.o: %.c
@echo "File: "$<
$(CC) -c $(CFLAGS) $< -o $@
clean:
rm -f $(OBJ)
So I was expecting that the OBJ variable in the main Makefile had a object files list but it is empty and I don't understand why. Isn't it including the common.mk file the same as copying it's content into the Makefile?
Thanks
makefile gnu-make
I want to use a common.mk file for common variable definitions and include this file in other Makefiles but in the first example I've done it is not working so I think that I have misunderstood something.
This is the Makefile:
CC=gcc
CFLAGS=-g -Wall
LIB_FLAGS=-L/usr/local/lib/ -lcgreen
BUILDDIR=$(CURDIR)/build
SRC=$(wildcard *.c)
export BUILDDIR
export CFLAGS
export LIB_FLAGS
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
unittests: dir externals $(OBJ)
@echo "SRC: $(SRC)"
@echo "OBJ: $(OBJ)" # THIS PRINTS OBJ AS EMPTY <------------------------------
$(CC) $(BUILDDIR)/*.o $(LIB_FLAGS) -o $(BUILDDIR)/unittests
$(BUILDDIR)/unittests
externals:
@$(MAKE) -C lib1 -f lib1.mk
dir:
mkdir -p $(BUILDDIR)
This is the common.mk file:
OBJ=$(patsubst %.c, $(BUILDDIR)/%.o, $(notdir $(SRC)))
$(BUILDDIR)/%.o: %.c
@echo "File: "$<
$(CC) -c $(CFLAGS) $< -o $@
clean:
rm -f $(OBJ)
So I was expecting that the OBJ variable in the main Makefile had a object files list but it is empty and I don't understand why. Isn't it including the common.mk file the same as copying it's content into the Makefile?
Thanks
makefile gnu-make
makefile gnu-make
asked Nov 19 at 19:10
jap jap
9911
9911
1
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
doesn't include anything. It starts with#
, so it's just a comment.
– melpomene
Nov 19 at 19:13
@melpomene Thanks.. I am used to C and didn't notice it.. two hours lost because of that! so embarrasing.. Ouch!
– jap jap
Nov 19 at 19:16
1
If you use an editor which has some sort of makefile editing mode it will show comments in a different color. It will also do better at handling TAB vs. spaces, typically. For debugging it can be helpful to add$(info ...)
functions into your makefiles to show variable values at various times etc. Adding these intocommon.mk
would have probably let you know that it wasn't being parsed at all, pretty quickly.
– MadScientist
Nov 19 at 19:21
add a comment |
1
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
doesn't include anything. It starts with#
, so it's just a comment.
– melpomene
Nov 19 at 19:13
@melpomene Thanks.. I am used to C and didn't notice it.. two hours lost because of that! so embarrasing.. Ouch!
– jap jap
Nov 19 at 19:16
1
If you use an editor which has some sort of makefile editing mode it will show comments in a different color. It will also do better at handling TAB vs. spaces, typically. For debugging it can be helpful to add$(info ...)
functions into your makefiles to show variable values at various times etc. Adding these intocommon.mk
would have probably let you know that it wasn't being parsed at all, pretty quickly.
– MadScientist
Nov 19 at 19:21
1
1
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
doesn't include anything. It starts with #
, so it's just a comment.– melpomene
Nov 19 at 19:13
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
doesn't include anything. It starts with #
, so it's just a comment.– melpomene
Nov 19 at 19:13
@melpomene Thanks.. I am used to C and didn't notice it.. two hours lost because of that! so embarrasing.. Ouch!
– jap jap
Nov 19 at 19:16
@melpomene Thanks.. I am used to C and didn't notice it.. two hours lost because of that! so embarrasing.. Ouch!
– jap jap
Nov 19 at 19:16
1
1
If you use an editor which has some sort of makefile editing mode it will show comments in a different color. It will also do better at handling TAB vs. spaces, typically. For debugging it can be helpful to add
$(info ...)
functions into your makefiles to show variable values at various times etc. Adding these into common.mk
would have probably let you know that it wasn't being parsed at all, pretty quickly.– MadScientist
Nov 19 at 19:21
If you use an editor which has some sort of makefile editing mode it will show comments in a different color. It will also do better at handling TAB vs. spaces, typically. For debugging it can be helpful to add
$(info ...)
functions into your makefiles to show variable values at various times etc. Adding these into common.mk
would have probably let you know that it wasn't being parsed at all, pretty quickly.– MadScientist
Nov 19 at 19:21
add a comment |
1 Answer
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As @melpomene pointed out I was including the file like it is done in C and therefore commenting it out!
Sorry for wasting your time..
add a comment |
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up vote
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down vote
As @melpomene pointed out I was including the file like it is done in C and therefore commenting it out!
Sorry for wasting your time..
add a comment |
up vote
0
down vote
As @melpomene pointed out I was including the file like it is done in C and therefore commenting it out!
Sorry for wasting your time..
add a comment |
up vote
0
down vote
up vote
0
down vote
As @melpomene pointed out I was including the file like it is done in C and therefore commenting it out!
Sorry for wasting your time..
As @melpomene pointed out I was including the file like it is done in C and therefore commenting it out!
Sorry for wasting your time..
answered Nov 19 at 19:19
jap jap
9911
9911
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1
#include common.mk # HERE I INCLUDE THE common.mk where OBJ is defined
doesn't include anything. It starts with#
, so it's just a comment.– melpomene
Nov 19 at 19:13
@melpomene Thanks.. I am used to C and didn't notice it.. two hours lost because of that! so embarrasing.. Ouch!
– jap jap
Nov 19 at 19:16
1
If you use an editor which has some sort of makefile editing mode it will show comments in a different color. It will also do better at handling TAB vs. spaces, typically. For debugging it can be helpful to add
$(info ...)
functions into your makefiles to show variable values at various times etc. Adding these intocommon.mk
would have probably let you know that it wasn't being parsed at all, pretty quickly.– MadScientist
Nov 19 at 19:21